Field of the Invention
The present invention relates to a chip arranging method for arranging plural chips.
Description of the Related Art
In recent years, manufacturing of packages that are obtained by forming a redistribution layer outside device chips (chips) by using a wafer-level redistribution technique and are called an FOWLP (Fan-Out Wafer Level Package) has been started (refer to e.g. Japanese Patent Laid-open No. 2013-58520). The FOWLP is advantageous for size reduction compared with existing packages using wire bonding or the like because the connection between the chip and a package substrate is established by a thin-film distribution layer.
For the manufacturing of the FOWLP, a process called a chip-first method is employed for example. In the chip-first method, first, chips arranged at arbitrary intervals are sealed by resin or the like to form a pseudo-wafer, and a distribution layer is provided on this pseudo-wafer. Thereafter, the pseudo-wafer is divided along planned dividing lines among the chips. Therefore, plural packages can be obtained.
Furthermore, a process called an RDL-first (Redistribution Layer-first) method is employed in some cases. In the RDL-first method, chips are arranged on a support wafer on which a distribution layer is provided and are sealed by resin or the like. Thereafter, the support wafer is removed and dividing into plural packages is performed. In this RDL-first method, for example, the chips can be so arranged as to avoid a faulty part of the distribution layer and thus the yield can be easily enhanced compared with the chip-first method.